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RISC-type designs often implement load/store+update as an "addressing mode", where the update part is an arbitrary offset (useful for scanning through small structs). x86 is somewat severely limited in that it can only scan scalars and only using the dedicated registers.
Hell, you can use any RISC-design register like a SP/BP – the day has come that the data content of the stack should be a
completely discrete memory block from the return-vector stack (with guard pages), if only to fully eliminate that particular exploit attack surface.